A number of digital system applications involve communicating data across asynchronous clock boundaries. A writer of data is controlled in a first clock domain, and the reader of the data is controlled in another clock domain that is asynchronous to the first clock domain. In some applications a FIFO may be used to buffer the data to be communicated from the writer to the reader. The FIFO includes a memory element, a write controller, and a read controller.
Writing to the memory is controlled within the clock domain of the writer, and data from the memory is read generally asynchronous to the writing of data to the memory. The writer uses a write pointer to address a memory location for writing data, and the reader uses a read pointer to address a memory location for reading data. The write pointer and read pointer are shared between the reader and the writer in order to avoid overwriting unread data in the memory and to avoid reading from an empty location in memory.
Some applications transmit packets of data in which the data in a packet is related. The data in a packet is typically delineated by “start” and “end” markers. Depending on system requirements, there may be multiple applications that receive the data provided by the reader. Some of the applications may process the same packet in different ways, or each individual application may be seeking packets of a certain type.
Packets may enter a system via a communications channel that is susceptible to introducing data errors. In response to detecting a data error or the loss of a communications link, the system will discard the packet being received. Waiting for the reader or reading application to detect a packet error, for example, finding a partial packet having only a “start marker” without a corresponding “end marker,” may result in wasted processing time by the reader. The wasting of time may be exacerbated if there are multiple applications receiving packet data. However, since the writer and reader are controlled in asynchronous clock domains and may write data to and read data from the memory at different rates, ensuring that the correct packet data is discarded without unduly delaying the flow of packets may be difficult.
The present invention may address one or more of the above issues.